The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2019

Filed:

Jan. 15, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventor:

Young-Gu Jin, Suwon-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); G01S 17/08 (2006.01); G01S 17/36 (2006.01); G01S 17/42 (2006.01); G01S 17/89 (2006.01); G01S 7/481 (2006.01); G01S 7/491 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14614 (2013.01); G01S 7/4816 (2013.01); G01S 7/4817 (2013.01); G01S 7/4914 (2013.01); G01S 7/4915 (2013.01); G01S 17/08 (2013.01); G01S 17/36 (2013.01); G01S 17/42 (2013.01); G01S 17/89 (2013.01); H01L 27/1461 (2013.01); H01L 27/1464 (2013.01); H01L 27/14627 (2013.01); H01L 27/14638 (2013.01);
Abstract

The image sensor includes: a semiconductor substrate having a first conductivity type and including a first surface, a second surface opposite to the first surface, and a well region adjacent to the first surface. A first vertical transfer gate and a second vertical transfer gate are spaced apart from each other and extend in a thickness direction of the semiconductor substrate from the first surface to pass through at least a part of the well region. A photoelectric conversion region has a second conductivity type, which is different from the first conductivity type, is located in the semiconductor substrate between the well region and the second surface, and overlaps the first vertical transfer gate and the second vertical transfer gate in the thickness direction of the semiconductor substrate. A wiring structure is located on the first surface of the semiconductor substrate.


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