The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2019

Filed:

May. 09, 2018
Applicant:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Gabriel Molas, Grenoble, FR;

Michel Harrand, Saint-Egreve, FR;

Elisa Vianello, Grenoble, FR;

Cécile Nail, Grenoble, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 29/02 (2006.01); G11C 11/56 (2006.01); H01L 27/10 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0069 (2013.01); G11C 11/5685 (2013.01); G11C 13/0007 (2013.01); G11C 13/0033 (2013.01); G11C 29/021 (2013.01); G11C 29/028 (2013.01); H01L 27/101 (2013.01); H01L 27/2436 (2013.01); G11C 13/0011 (2013.01); G11C 2013/009 (2013.01); G11C 2013/0076 (2013.01); G11C 2013/0092 (2013.01);
Abstract

A method for managing the endurance of a non-volatile rewritable memory including memory cells each including an ordered stack of a lower electrode, a layer of dielectric material and an upper electrode, the dielectric material switching between a high resistance state and a low resistance state, or vice versa, to enable a writing in the memory cell or an erasure of the memory cell. The method includes at the end of each writing and erasure cycle, reading the erasure conditions of the memory cell in the course of the final erasure operation of the cycle, and comparing the read erasure conditions with a predetermined median erasure value corresponding to a median resistance value which follows a predetermined dependency law linking the condition of erasure of a cycle with the condition of writing of a following cycle; and determining the writing conditions from the results of the comparison.


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