The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2019

Filed:

Aug. 02, 2017
Applicant:

Celerint, Llc, New York, NY (US);

Inventor:

Howard H. Roberts, Jr., Austin, TX (US);

Assignee:

CELERINT, LLC, New York, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/26 (2014.01); G01R 1/04 (2006.01); G01R 31/28 (2006.01); G11C 29/56 (2006.01); H01L 21/687 (2006.01); G11C 29/50 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2601 (2013.01); G01R 1/04 (2013.01); G01R 1/0458 (2013.01); G01R 31/26 (2013.01); G01R 31/287 (2013.01); G01R 31/2837 (2013.01); G01R 31/2849 (2013.01); G01R 31/2867 (2013.01); G01R 31/2874 (2013.01); G01R 31/2882 (2013.01); G11C 29/56008 (2013.01); G11C 29/56012 (2013.01); G11C 29/56016 (2013.01); H01L 21/68707 (2013.01); G11C 2029/5002 (2013.01);
Abstract

A method is provided for performing continuous single insertion semiconductor testing of a group of semiconductors that are divided into a first subgroup and a second subgroup at multiple different temperatures. The single insertion semiconductor testing is performed by sequentially executing testing cycles, characterized by the tester alternately executing temperature testing periods and temperature ramping periods for the first subgroup, while simultaneously executing temperature ramping periods and temperature testing periods for the second subgroup. The temperature testing periods operate at two or more different temperatures. The single insertion testing sequence entirely eliminates tester index time when the testing time is equal to or greater than the ramping times, and substantially reduces tester index time when the testing time is less that the ramping times.


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