The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2019

Filed:

Jul. 13, 2018
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Rajeev Sharma, Oceanside, CA (US);

Santhosh Kumar Gude, San Jose, CA (US);

Parth Patel, San Diego, CA (US);

Hadi Goudarzi, San Diego, CA (US);

Eskinder Hailu, Cary, NC (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H04L 7/033 (2006.01); G06F 1/26 (2006.01); G06F 13/362 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0331 (2013.01); G06F 1/266 (2013.01); G06F 13/362 (2013.01);
Abstract

A desirable feature of a SERDES design is power savings. One way to achieve power savings is by keeping the CDR circuit OFF during most of the time when a link is active between a transmitter and a receiver. However, due to voltage supply noise, temperature fluctuations and uncorrelated crosstalk, the receiver data may shift and/or the eye may collapse if the CDR is not turned ON to take care of these modulations. To address such disadvantages, it is proposed to generate a CDR profile that can specify optimum CDR ON and OFF time so that link stability may be maintained while saving power.


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