The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 13, 2019
Filed:
Mar. 22, 2018
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventor:
Robert Callaghan Taft, Munich, DE;
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/01 (2006.01); H03K 3/037 (2006.01); G06F 1/12 (2006.01); H03K 19/21 (2006.01); H03K 5/15 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/01 (2013.01); G06F 1/12 (2013.01); H03K 3/037 (2013.01); H03K 3/0375 (2013.01); H03K 5/15046 (2013.01); H03K 5/15066 (2013.01); H03K 19/21 (2013.01); H03K 2005/00078 (2013.01);
Abstract
A circuit includes a plurality of series-coupled delay buffers and a plurality of logic gates. Each logic gate includes first and second inputs. The first input of each logic gate is coupled to a corresponding one of the delay buffers. The circuit also includes a plurality of flip-flops. Each flip-flop includes a data input and a data output. The data input is coupled to an output of a corresponding one of the logic gates and the data output is coupled to the second input of one of the corresponding logic gates.