The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2019

Filed:

Jan. 23, 2018
Applicant:

Canon Kabushiki Kaisha, Tokyo, JP;

Inventor:

Ginjiro Toyoguchi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); G01C 3/08 (2006.01); G01J 1/44 (2006.01); H04N 5/355 (2011.01); B60W 30/09 (2012.01); B60W 50/14 (2012.01);
U.S. Cl.
CPC ...
H01L 27/1461 (2013.01); G01C 3/085 (2013.01); G01J 1/44 (2013.01); H04N 5/3559 (2013.01); B60W 30/09 (2013.01); B60W 50/14 (2013.01); B60W 2050/143 (2013.01); B60W 2420/42 (2013.01); B60W 2510/20 (2013.01); B60W 2520/10 (2013.01); B60W 2520/14 (2013.01); B60W 2710/0677 (2013.01); B60W 2710/18 (2013.01); G01J 2001/448 (2013.01);
Abstract

A solid-state imaging device includes a plurality of pixels each including a photoelectric converter that generates charges by photoelectric conversion and a charge holding portion that holds charges transferred from the photoelectric converter. The photoelectric converter includes a first semiconductor region of a first conductivity type provided in a surface portion of a semiconductor substrate, a second semiconductor region of a second conductivity type provided under the first semiconductor region and configured to accumulate generated charges, a third semiconductor region of the first conductivity type provided under the second semiconductor region, and a fourth semiconductor region of the first conductivity type provided in a part of a portion between the first and second semiconductor regions. In a plan view, the second semiconductor region has a first region not overlapping with the third semiconductor region, and the fourth semiconductor region overlaps with at least a part of the first region.


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