The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2019

Filed:

Dec. 21, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Hong-sik Shin, Seoul, KR;

Do-hyoung Kim, Hwaseong-si, KR;

Doo-young Lee, Seoul, KR;

Hyon-wook Ra, Hwaseong-si, KR;

Seo-bum Lee, Seoul, KR;

Won-hyuk Lee, Incheon, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 29/78 (2006.01); H01L 49/02 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0629 (2013.01); H01L 21/76805 (2013.01); H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 23/5226 (2013.01); H01L 23/5228 (2013.01); H01L 23/5283 (2013.01); H01L 23/53295 (2013.01); H01L 28/24 (2013.01); H01L 29/785 (2013.01);
Abstract

Provided is a semiconductor device having an enhanced characteristic and a resistor structure satisfying a desired target resistor value of a resistor device. A semiconductor device includes: a lower interlayer insulating layer disposed on a substrate comprising a resistor area; a resistor structure comprising a resistor layer and an etch stop pattern sequentially stacked on the lower interlayer insulating layer of the resistor area; an upper interlayer insulating layer configured to cover the resistor structure and disposed on the lower interlayer insulating layer; a resistor contact structure configured to pass through the upper interlayer insulating layer and the etch stop pattern and contact the resistor layer; and a resistor contact spacer disposed between the upper interlayer insulating layer, the etch stop pattern, and the resistor contact structure.


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