The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2019

Filed:

Oct. 06, 2016
Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Venkatesh P. Ramachandra, San Jose, CA (US);

Michael Mostovoy, San Ramon, CA (US);

Hem Takiar, Fremont, CA (US);

Gokul Kumar, San Jose, CA (US);

Vinayak Ghatawade, Bangalore, IN;

Assignee:

SanDisk Technologies LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 25/18 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 29/00 (2006.01); G11C 7/06 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); G11C 5/04 (2006.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); G06F 13/4018 (2013.01); G06F 13/4234 (2013.01); G11C 5/04 (2013.01); G11C 5/063 (2013.01); G11C 5/066 (2013.01); G11C 7/065 (2013.01); G11C 7/10 (2013.01); G11C 7/22 (2013.01); G11C 29/781 (2013.01); H01L 25/18 (2013.01); G11C 2207/105 (2013.01); G11C 2207/108 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06582 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01);
Abstract

A non-volatile storage system includes a plurality of memory dies and an interface circuit. Each memory die includes a wide I/O interface electrically coupled to another wide I/O interface of another memory die of the plurality of memory dies. The interface circuit is physically separate from the memory dies. The interface circuit includes a first interface and a second interface. The first interface comprises a wide I/O interface electrically coupled to a wide I/O interface of at least one of the memory dies of the plurality of memory dies. The second interface is a narrow I/O interface configured to communicate with an external circuit.


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