IDiyas

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10381279 B1

PDFFull Text
Date of Patent:
Aug. 13, 2019

Filed:

Oct. 30, 2017

Method of manufacturing semiconductor device and semiconductor device

Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Akira Yajima, Ibaraki, JP;

Assignee:

RENESAS ELECTRONICS CORPORATION, Tokyo, JP;

Attorney:

McDermott Will & Emery LLP

Primary Examiner:

Tong-Ho Kim

Int. Cl.
CPC ...
H01L 21/66 (2006.01); G11C 29/48 (2006.01); H01L 25/065 (2006.01); H01L 21/324 (2006.01); H01L 21/4763 (2006.01); G11C 29/06 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); G11C 29/56 (2006.01);
U.S. Cl.
CPC ...
H01L 22/32 (2013.01); G11C 29/06 (2013.01); G11C 29/48 (2013.01); H01L 21/324 (2013.01); H01L 21/47635 (2013.01); H01L 22/14 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/11 (2013.01); H01L 24/14 (2013.01); H01L 24/43 (2013.01); H01L 24/49 (2013.01); H01L 24/85 (2013.01); H01L 25/0655 (2013.01); H01L 25/0657 (2013.01); G11C 2029/5602 (2013.01); H01L 23/3192 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/02311 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/02377 (2013.01); H01L 2224/03009 (2013.01); H01L 2224/0392 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05022 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05186 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/05554 (2013.01); H01L 2224/05567 (2013.01); H01L 2224/05583 (2013.01); H01L 2224/05655 (2013.01); H01L 2224/05686 (2013.01); H01L 2224/06102 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13021 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/451 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48138 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73207 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/04941 (2013.01);
Abstract

To enhance reliability of a test by suppressing defective bonding of a solder in the test of a semiconductor device, a method of manufacturing the semiconductor device includes: preparing a semiconductor wafer that includes a first pad electrode provided with a first cap film and a second pad electrode provided with a second cap film. Further, a polyimide layer that includes a first opening on the first pad electrode and a second opening on the second pad electrode is formed, and then, a rearrangement wiring that is connected to the second pad electrode via the second opening is formed. Next, an opening is formed in the polyimide layer such that an organic reaction layer remains on each of the first pad electrode and a bump land of the rearrangement wiring, then heat processing is performed on the semiconductor wafer, and then, a bump is formed on the rearrangement wiring.

Find Patent Forward Citations

Loading…