The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2019

Filed:

Mar. 05, 2018
Applicant:

Stmicroelectronics (Crolles 2) Sas, Crolles, FR;

Inventors:

Pascal Chevalier, Chapareillan, FR;

Gregory Avenier, Saint Nazaire les Eymes, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/102 (2006.01); H01L 21/8228 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/732 (2006.01); H01L 27/06 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/285 (2006.01); H01L 21/311 (2006.01); H01L 21/761 (2006.01); H01L 21/8249 (2006.01); H01L 27/082 (2006.01);
U.S. Cl.
CPC ...
H01L 21/82285 (2013.01); H01L 21/02532 (2013.01); H01L 21/02639 (2013.01); H01L 21/26513 (2013.01); H01L 21/28518 (2013.01); H01L 21/31111 (2013.01); H01L 21/761 (2013.01); H01L 21/8249 (2013.01); H01L 27/0623 (2013.01); H01L 27/0826 (2013.01); H01L 27/1022 (2013.01); H01L 29/0649 (2013.01); H01L 29/0804 (2013.01); H01L 29/0821 (2013.01); H01L 29/42304 (2013.01); H01L 29/66272 (2013.01); H01L 29/732 (2013.01); H01L 29/0646 (2013.01);
Abstract

A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type doped semiconductor substrate and divided into first, second, and third regions, with the third region forming the base. An insulating well is deeply implanted into the substrate. First and second third wells, respectively of N-type and P-type are formed to extend between the second region and third region and the insulating well. A third well of P-type is formed below the third region to provide the collector. Insulating layers are deposited over the third region and patterned to form an opening. Epitaxial growth of a second P-type doped semiconductor layer is performed in the opening to provide the emitter.


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