The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2019

Filed:

Jan. 10, 2018
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Anthony Correale, Jr., Raleigh, NC (US);

Philip Michael Iles, Durham, NC (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 23/00 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5077 (2013.01); H01L 23/5286 (2013.01); G06F 17/5072 (2013.01); G06F 17/5081 (2013.01); G06F 2217/78 (2013.01);
Abstract

Power distribution networks (PDNs) using hybrid grid and pillar arrangements are disclosed. In particular, a process for designing an integrated circuit (IC) considers various design criteria when placing and routing the PDN for the IC. Exemplary design criteria include switching frequencies, current densities, and decoupling capacitance and their impact on temperature. In areas of high localized temperature, a power grid structure is used. In other areas, shared metal track pillars may be used. By mixing power grids with pillars, the IC may reduce local hotspots by allowing the grid to help dissipate heat and assist with decoupling capacitance while at the same time providing pillars in areas of high current density to reduce resistive losses.


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