The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 13, 2019
Filed:
Mar. 29, 2017
Silicon Technologies, Inc., Holladay, UT (US);
Thomas L. Wolf, Salt Lake City, UT (US);
Kent F. Smith, Holladay, UT (US);
Tracy L. Johancsik, Murray, UT (US);
Kyler C. Fillerup, Orem, UT (US);
Thomas G. Wolf, Bloomington, IN (US);
Silicon Technologies, Inc., Holladay, UT (US);
Abstract
A method for designing an semiconductor integrated circuit is disclosed, including generating a physical layout from a schematic layout of the analog integrated circuit. The method comprises retrieving, with a processor, pre-defined cells having physical layout information for a specific process stored in a memory device responsive to the schematic layout being created by a circuit designer using an analog circuit design tool, building the physical layout by connecting the retrieved pre-defined cells according to the schematic layout, and storing the physical layout in the memory device. Related systems and computer-readable media are also described herein.