The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2019

Filed:

Sep. 29, 2016
Applicant:

Friday Harbor Llc, New York, NY (US);

Inventors:

Jerome Vincent Coffin, San Diego, CA (US);

Douglas A. Palmer, San Diego, CA (US);

Assignee:

Friday Harbor LLC, New York, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/10 (2016.01); H04L 12/863 (2013.01); H04L 12/911 (2013.01); H04L 29/06 (2006.01); H04L 12/913 (2013.01); H04L 12/937 (2013.01); H04L 12/935 (2013.01); H04L 12/931 (2013.01); H04L 12/721 (2013.01); H04L 12/741 (2013.01); G06F 12/1081 (2016.01); G06F 12/109 (2016.01);
U.S. Cl.
CPC ...
G06F 12/10 (2013.01); G06F 12/109 (2013.01); G06F 12/1081 (2013.01); H04L 45/566 (2013.01); H04L 45/74 (2013.01); H04L 47/627 (2013.01); H04L 47/724 (2013.01); H04L 47/726 (2013.01); H04L 49/254 (2013.01); H04L 49/3027 (2013.01); H04L 49/70 (2013.01); H04L 69/22 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/152 (2013.01); G06F 2212/657 (2013.01);
Abstract

An improved virtual memory scheme designed for multi-processor environments that uses processor registers and a small amount of dedicated logic to eliminate the overhead that is associated with the use of page tables. The virtual addressing provides a contiguous virtual address space where the actual real memory is distributed across multiple memories. Locally, within an individual memory, the virtual space may be composed of discontinuous 'real' segments or 'chunks' within the memory, allowing bad blocks of memory to be bypassed without alteration of the virtual addresses. The delays and additional bus traffic associated with translating from virtual to real addresses are substantially reduced or eliminated.


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