The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2019

Filed:

Jul. 17, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ekaterina M. Ambroladze, Los Angeles, CA (US);

Timothy C. Bronson, Round Rock, TX (US);

Matthias Klein, Wappingers Falls, NY (US);

Pak-kin Mak, Poughkeepsie, NY (US);

Vesselina K. Papazova, Highland, NY (US);

Robert J. Sonnelitter, III, Wappingers Falls, NY (US);

Lahiruka S. Winter, Fishkill, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 12/0831 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0831 (2013.01); G06F 13/1615 (2013.01); G06F 2212/60 (2013.01); G06F 2212/621 (2013.01);
Abstract

Embodiments include methods, systems and computer program products method for maintaining ordered memory access with parallel access data streams associated with a distributed shared memory system. The computer-implemented method includes performing, by a first cache, a key check, the key check being associated with a first ordered data store. A first memory node signals that the first memory node is ready to begin pipelining of a second ordered data store into the first memory node to an input/output (I/O) controller. A second cache returns a key response to the first cache indicating that the pipelining of the second ordered data store can proceed. The first memory node sends a ready signal indicating that the first memory node is ready to continue pipelining of the second ordered data store into the first memory node to the I/O controller, wherein the ready signal is triggered by receipt of the key response.


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