The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2019

Filed:

Sep. 20, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

William L. Brodsky, Binghamton, NY (US);

Silvio Dragone, Olten, CH;

Roger S. Krabbenhoft, Rochester, MN (US);

David C. Long, Wappingers Falls, NY (US);

Stefano S. Oggioni, Milan, IT;

Michael T. Peets, Staatsburg, NY (US);

William Santiago-Fernandez, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); G01D 5/16 (2006.01); H05K 1/18 (2006.01); H05K 3/30 (2006.01); H05K 3/32 (2006.01);
U.S. Cl.
CPC ...
G01D 5/16 (2013.01); H05K 1/0275 (2013.01); H05K 1/0298 (2013.01); H05K 1/182 (2013.01); H05K 3/30 (2013.01); H05K 3/32 (2013.01); H05K 2201/096 (2013.01); H05K 2201/09263 (2013.01); H05K 2201/10151 (2013.01); H05K 2201/10371 (2013.01);
Abstract

Methods of fabricating electronic circuits and electronic packages are provided. The electronic circuit includes a multilayer circuit board, and a tamper-respondent sensor embedded within the circuit board. The tamper-respondent sensor defines, at least in part, a secure volume associated with the multilayer circuit board. In certain implementations, the tamper-respondent sensor includes multiple tamper-respondent layers embedded within the circuit board including, for instance, one or more tamper-respondent frames and one or more tamper-respondent mat layers, with the tamper-respondent frame(s) being disposed, at least in part, above the tamper-respondent mat layer(s), which together define the secure volume where extending into the multilayer circuit board. In certain embodiments, one or more of the tamper-respondent layers are divided into multiple, separate tamper-respondent circuit zones, with the tamper-respondent layers, including the circuit zones, being electrically connected to monitor circuitry within the secure volume.


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