The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2019

Filed:

May. 31, 2016
Applicant:

Veritas Technologies Llc, Mountain View, CA (US);

Inventors:

Adhiraj Joshi, Pune, IN;

Abhijit Toley, Pune, IN;

Assignee:

Veritas Technologies LLC, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 29/08 (2006.01); G06F 3/06 (2006.01); G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
H04L 67/1097 (2013.01); G06F 3/061 (2013.01); G06F 3/067 (2013.01); G06F 3/0659 (2013.01); G06F 13/28 (2013.01); H04L 67/2842 (2013.01); G06F 2213/2806 (2013.01);
Abstract

Disclosed herein are systems, methods, and processes to improve throughput in OpenFabrics and Remote Direct Memory Access (RDMA) computing environments. Data and a header is received. Buffers in which the data and the header are to be written are identified. Placement information for the data and the header is determined based on a size of each buffer, a page-boundary-alignment of the data, and a header alignment of the header. The data and the header are written to the buffer(s) using the placement information. In such computing environments, throughout can be improved by writing data on page boundaries and the header on a header boundary in a second to last buffer.


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