The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 06, 2019
Filed:
Jul. 18, 2017
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;
Inventors:
Jiyoup Kim, Suwon-si, KR;
Dong-Min Shin, Seoul, KR;
Beomkyu Shin, Seongnam-si, KR;
Junjin Kong, Yongin-si, KR;
Hong Rak Son, Anyang-si, KR;
Assignee:
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G11C 11/56 (2006.01); G11C 29/52 (2006.01); H03M 13/00 (2006.01); H03M 13/11 (2006.01); H03M 13/37 (2006.01);
U.S. Cl.
CPC ...
H03M 13/1111 (2013.01); G06F 11/1012 (2013.01); G06F 11/1068 (2013.01); G11C 11/5642 (2013.01); G11C 29/52 (2013.01); H03M 13/1108 (2013.01); H03M 13/3707 (2013.01); H03M 13/3723 (2013.01); H03M 13/3746 (2013.01); H03M 13/6325 (2013.01); H03M 13/116 (2013.01); H03M 13/1188 (2013.01);
Abstract
A low-density parity check (LDPC) decoder may include a variable node processing unit and a check node processing unit. The check node processing unit includes memory elements storing a check node value. The memory elements are interconnected through two or more paths, and each of the paths may include a total or partial cyclic permutation of the memory elements to transmit the check node value.