The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2019

Filed:

Dec. 27, 2017
Applicant:

Realtek Semiconductor Corporation, Hsinchu, TW;

Inventors:

Shih-Hsiung Huang, Miaoli County, TW;

Sheng-Hsiung Lin, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/66 (2006.01); H03M 1/80 (2006.01); H03M 1/68 (2006.01); H03M 1/46 (2006.01);
U.S. Cl.
CPC ...
H03M 1/802 (2013.01); H03M 1/68 (2013.01); H03M 1/468 (2013.01);
Abstract

The present invention discloses a capacitor layout of a digital-to-analog conversion integrated circuit (DAC IC), comprising a first capacitor group, a second capacitor group and a third capacitor group. The first capacitor group, located within an interior layout area of the capacitor layout, determines a most significant bit (MSB) of the DAC IC and includes a plurality of capacitor units coupled between a first upper circuit and a first lower circuit. The second capacitor group, located within the interior layout area, determines a non-MSB bit of the DAC IC and includes at least one capacitor unit(s) coupled between a second upper circuit and a second lower circuit. The third capacitor group includes a plurality of capacitor units coupled between a third upper circuit and a third lower circuit which are not short-circuited; the capacitor units of the third capacitor group are disposed around the interior layout area.


Find Patent Forward Citations

Huang, Shih-Hsiung. (2019). Capacitor layout of digital-to-analog conversion integrated circuit (U.S. Patent No. 10374625). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10374625

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…