The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2019

Filed:

Sep. 27, 2017
Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventors:

Po-Chun Huang, Yilan County, TW;

Chao-Ching Hung, Changhua County, TW;

Yu-Li Hsueh, New Taipei, TW;

Pang-Ning Chen, Taipei, TW;

Assignee:

MEDIATEK INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 5/12 (2006.01); H03K 5/15 (2006.01); H03K 21/02 (2006.01); H04B 1/04 (2006.01);
U.S. Cl.
CPC ...
H03K 5/15046 (2013.01); H03K 21/026 (2013.01); H04B 1/04 (2013.01);
Abstract

A quadrature clock generating apparatus connected to a local oscillator generating an input clock signal and an inverted input clock signal includes a fractional dividing circuit and a quadrature signal generating circuit. The fractional dividing circuit is configured for receiving the input clock signal and the inverted input clock signal, and for performing frequency-division upon the input clock signal and the inverted input clock signal to generate a frequency-divided clock signal according to a fractional dividing parameter. The quadrature signal generating circuit is configured for receiving the input clock signal, the inverted input clock signal, and the frequency-divided clock signal to generate a plurality of quadrature clock signals.


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