The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2019

Filed:

Mar. 04, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Dong-hun Lee, Anyang-si, KR;

Dong-won Kim, Seongnam-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 27/11 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); G11C 11/419 (2006.01); H01L 27/146 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 27/11578 (2017.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78696 (2013.01); G11C 11/419 (2013.01); H01L 27/1104 (2013.01); H01L 27/14616 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 27/11578 (2013.01); H01L 29/1037 (2013.01); H01L 29/66787 (2013.01); H01L 29/785 (2013.01);
Abstract

A static random access memory (SRAM) device includes a circuit element that includes a first inverter having a first load transistor and a first drive transistor and a second inverter having a second load transistor and a second drive transistor. Input and output nodes of the first inverter and the second inverter are cross-connected to each other. A first transfer transistor is connected to the output node of the first inverter, and a second transfer transistor is connected to the output nodes of the second inverter. Each of the first and second load transistors, the first and second drive transistors, and the first and second transfer transistors includes a transistor having multi-bridge channels. At least one of the first and second load transistors, the first and second drive transistors, and the first and second transfer transistors includes a transistor having a different number of multi-bridge channels from the other transistors.


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