The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2019

Filed:

Dec. 05, 2016
Applicant:

The Regents of the University of California, Oakland, CA (US);

Inventor:

Chenming Hu, Oakland, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/786 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/778 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78391 (2014.09); H01L 29/42392 (2013.01); H01L 29/516 (2013.01); H01L 29/6684 (2013.01); H01L 29/775 (2013.01); H01L 29/778 (2013.01); H01L 29/785 (2013.01); H01L 29/78696 (2013.01);
Abstract

A three-dimensional (3D) transistor includes a ferroelectric film between the gate and the channel. The 3D transistor can be characterized as a 3D Negative Capacitance (NC) transistor due to the negative capacitance resulting from the ferroelectric film. Performance of the transistor is optimized by manipulating the structure and/or by the selection of materials. In one example, the capacitance of the ferroelectric film (C) is matched to the sum of the gate capacitance (C) and the gate edge capacitance (C), wherein the gate edge capacitance (C) is the capacitance at the edge of the gate and between the gate and the source and its extension, and the gate and the drain and its extension.


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