The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2019

Filed:

Feb. 06, 2018
Applicant:

Rohm Co., Ltd., Kyoto, JP;

Inventors:

Hajime Okuda, Kyoto, JP;

Adrian Joita, Kyoto, JP;

Assignee:

ROHM CO., LTD., Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/739 (2006.01); H01L 27/092 (2006.01); H01L 21/265 (2006.01); H01L 29/40 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4236 (2013.01); H01L 21/26586 (2013.01); H01L 27/092 (2013.01); H01L 27/0922 (2013.01); H01L 29/407 (2013.01); H01L 29/42376 (2013.01); H01L 29/66348 (2013.01); H01L 29/66734 (2013.01); H01L 29/7397 (2013.01); H01L 29/7813 (2013.01); H01L 29/083 (2013.01); H01L 29/1095 (2013.01);
Abstract

A semiconductor device includes a semiconductor layer of a first conductivity type having a main surface at which a trench is formed, a gate insulating layer formed along a side wall of the trench, a gate electrode embedded in the trench with the gate insulating layer interposed therebetween and having an upper surface located below the main surface of the semiconductor layer, a second conductivity type region formed in a surface layer portion of the main surface of the semiconductor layer and facing the gate electrode with the gate insulating layer interposed therebetween, a first conductivity type region formed in a surface layer portion of the second conductivity type region and facing the gate electrode with the gate insulating layer interposed therebetween, and a side wall insulating layer covering the side wall of the trench in a recessed portion defined by the side wall of the trench and the upper surface of the gate electrode.


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