The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2019

Filed:

Dec. 21, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Yulong Li, Westchester, NY (US);

Paul M. Solomon, Westchester, NY (US);

Siyuranga Koswatta, Carmel, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/68 (2006.01); H01L 29/49 (2006.01); H01L 29/205 (2006.01); H01L 29/80 (2006.01); H01L 29/78 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1045 (2013.01); H01L 29/0646 (2013.01); H01L 29/1054 (2013.01); H01L 29/205 (2013.01); H01L 29/4983 (2013.01); H01L 29/66431 (2013.01); H01L 29/66659 (2013.01); H01L 29/66977 (2013.01); H01L 29/685 (2013.01); H01L 29/802 (2013.01); H01L 29/6684 (2013.01); H01L 29/66825 (2013.01); H01L 29/788 (2013.01); H01L 29/78391 (2014.09);
Abstract

Embodiments of the invention are directed to a method and resulting structures for a semiconductor device having a controllable resistance. An example method for forming a semiconductor device includes forming a source terminal and a drain terminal of a field effect transistor (FET) on a substrate. The source terminal and the drain terminal are formed on either sides of a channel region. An energy barrier is formed adjacent to the source terminal and the channel region. A conductive gate is formed over the channel region.


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