The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2019

Filed:

Jul. 10, 2014
Applicant:

Institute of Microelectronics, Chinese Academy of Sciences, Chaoyang, District, Bejing, CN;

Inventor:

Zongliang Huo, Bejing, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11556 (2017.01); H01L 29/10 (2006.01); H01L 29/788 (2006.01); H01L 27/11582 (2017.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); H01L 29/1037 (2013.01); H01L 29/7887 (2013.01); H01L 29/7889 (2013.01); H01L 27/11582 (2013.01); H01L 29/7926 (2013.01);
Abstract

A 3-D semiconductor device comprising a plurality of memory cells and a plurality of selection transistors, each of said plurality of memory cells comprises: a channel layer, distributed along a direction perpendicular to the substrate surface; a plurality of inter-layer insulating layers and a plurality of gate stack structures, alternately laminating along the sidewall of the channel layer; a plurality of floating gates, located between the plurality of inter-layer insulating layers and the sidewall of the channel layer; a plurality of drains, located at the top of the channel layer; and a plurality of sources, located in the said substrate between two adjacent memory cells of the said plurality of memory cells.


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