The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 06, 2019
Filed:
Dec. 01, 2017
Applicant:
Globalfoundries Inc., Grand Cayman, KY;
Inventors:
Ram Asra, Clifton Park, NY (US);
Mohit Bajaj, Bangalore, IN;
Edward Nowak, Shelburne, VT (US);
Kota V. R. M. Murali, Shrub Oak, NY (US);
Assignee:
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 27/02 (2006.01); H01L 29/78 (2006.01); H01L 27/11 (2006.01); H01L 29/06 (2006.01); H01L 27/092 (2006.01); H01L 27/12 (2006.01); H01L 21/8238 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 27/1104 (2013.01); H01L 27/1211 (2013.01); H01L 29/0649 (2013.01); H01L 29/42356 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract
A method of forming a SRAM semiconductor device with reduced area layout and a resulting device are provided. Embodiments include forming a first field effect transistor (FET) over a substrate; forming an insulating material over the first FET; forming a second FET over the insulating material; and patterning the first FET, insulating material and second FET to form fins over the substrate.