The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 06, 2019
Filed:
May. 11, 2017
International Business Machines Corporation, Armonk, NY (US);
Nathan Buck, Underhill, VT (US);
Sean M. Carey, Hyde Park, NY (US);
Peter C. Elmendorf, Poughkeepsie, NY (US);
Eric A. Foreman, Fairfax, VT (US);
Jeffrey G. Hemmett, St. George, VT (US);
Lyle Jackson, Poughkeepsie, NY (US);
Kerim Kalafala, Rhinebeck, NY (US);
Stephen G. Shuma, Underhill, VT (US);
Michael H. Wood, Hopewell Junction, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A design and timing model for at least one circuit path of at least a portion of an IC design is loaded into a computer. At least one canonical clock variable associated with the model is defined; it includes at least one source of variation. The computer is used to perform an SSTA of the at least one circuit path, based on the design and timing model and the at least one canonical clock variable, to obtain slack canonical data. A clock period is projected, based on the slack canonical data, such that a cycle time canonical is projected to a different space than a logic canonical. Results of the SSTA and the projected clock period are output to determine performance compliance. Efficient operation of the computer is enhanced by analyzing a slack vector in a single timing run, loaded once, and multithreading timing propagation.