The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2019

Filed:

Jun. 07, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

Jee-Seok Hyun, Hwaseong-si, KR;

Keonsoo Ha, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/10 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1096 (2013.01); G06F 3/061 (2013.01); G06F 3/0619 (2013.01); G06F 3/0656 (2013.01); G06F 3/0665 (2013.01); G06F 3/0689 (2013.01);
Abstract

A storage device includes a plurality of first memories, a controller, and a second memory. The controller controls the first memories such that first and second data chunks associated with target data are distributively stored in the plurality of first memories. The controller generates a first intermediate parity using the first data chunk, which is processed immediately before the second data chunk. When the second data chunk is not a data chunk which is processed last in connection with the target data and the first intermediate parity is buffered in the second memory, the controller generates a second intermediate parity using the first intermediate parity buffered in the second memory and the second data chunk, and outputs the second intermediate parity to the second memory to be buffered.


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