The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2019

Filed:

May. 04, 2017
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Jawaharlal Tangudu, Bangalore, IN;

Suvam Nandi, Bangalore, IN;

Pooja Sundar, Bangalore, IN;

Jaiganesh Balakrishnan, Bangalore, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/533 (2006.01); G06F 7/523 (2006.01); G06F 7/50 (2006.01); H03D 7/16 (2006.01);
U.S. Cl.
CPC ...
G06F 7/523 (2013.01); G06F 7/50 (2013.01); H03D 7/161 (2013.01);
Abstract

A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.


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