The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2019

Filed:

Dec. 29, 2016
Applicant:

Western Digital Technologies, Inc., Irvine, CA (US);

Inventors:

Parvaneh Alavi, Lake Forest, CA (US);

Hung-min Chang, Irvine, CA (US);

Haining Liu, Irvine, CA (US);

Jerry Lo, Hacienda Heights, CA (US);

Hung-Cheng Yeh, Irvine, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 3/06 (2006.01); G11C 16/34 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0679 (2013.01); G06F 3/064 (2013.01); G06F 3/0616 (2013.01); G06F 11/004 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01); G11C 16/349 (2013.01); G11C 16/3418 (2013.01); G11C 16/3427 (2013.01); G11C 16/3431 (2013.01); G06F 2201/81 (2013.01); G06F 2201/88 (2013.01);
Abstract

Aspects of the disclosure provide methods and apparatus that monitor and mitigate Read Disturb errors in non-volatile memory (NVM) devices such as NAND flash memories. The disclosed methods and apparatus determine which logical block addresses (LBAs) in the NVM device are frequently accessed by a host, rather than looking a physical address accesses. The potential Read Disturb errors may then be mitigated by triggering Read Disturb mitigation when the numbers of access of one or more of the frequently accessed LBAs exceeds a predefined number of accesses.


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