The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 2019

Filed:

Jul. 21, 2017
Applicant:

SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;

Inventors:

Sungchun Jang, Icheon-si, KR;

Kyung Whan Kim, Seoul, KR;

Dong Kyun Kim, Cheongju-si, KR;

Assignee:

SK hynix Inc., Icheon-si Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/14 (2014.01); H03L 7/08 (2006.01); H03L 7/099 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/14 (2013.01); H03L 7/0805 (2013.01); H03L 7/0998 (2013.01); H03K 2005/00052 (2013.01);
Abstract

An internal clock generation circuit includes an interpolation clock generation circuit and a locked clock generation circuit. The interpolation clock generation circuit generates an interpolation clock signal from a division clock signal in response to a switching control signal and a current control signal. The locked clock generation circuit includes an oscillator and generates a locked clock signal for generating an internal clock signal from the interpolation clock signal.


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