The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 2019

Filed:

Aug. 28, 2018
Applicant:

Ferric Inc., New York, NY (US);

Inventors:

Noah Sturcken, New York, NY (US);

Ehsan Kalami, Novi, MI (US);

Joseph Meyer, Plainsboro, NJ (US);

Michael Lekas, New York, NY (US);

Assignee:

Ferric Inc., New York, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 3/156 (2006.01); H01F 27/28 (2006.01); H01F 27/24 (2006.01); H05K 1/02 (2006.01);
U.S. Cl.
CPC ...
H02M 3/156 (2013.01); H01F 27/24 (2013.01); H01F 27/2804 (2013.01); H01F 27/2823 (2013.01); H05K 1/0298 (2013.01); H05K 2201/086 (2013.01);
Abstract

A power management module comprises one or more power converter chips that are mounted on a power management package substrate. First and second electrical contacts are disposed on opposing first and second sides of the power management package substrate. The power management module can be mounted on a processor module to supply power to one or more processor chips in the processor module. In one example, the processor chip(s) are mounted on a first side of a processor package substrate and the power management module is mounted on an opposing second side of the processor package substrate. The power management module and the processor module can be centered and aligned with respect to each other or they can be offset laterally from each other. In another embodiment, the power management module and the processor chip(s) are mounted on the same side of the processor package substrate.


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