The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 2019

Filed:

Sep. 08, 2017
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Takashi Fukushima, Yokkaichi, JP;

Katsuyuki Sekine, Yokkaichi, JP;

Satoshi Nagashima, Yokkaichi, JP;

Hisataka Meguro, Yokkaichi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 21/3105 (2006.01); H01L 27/1157 (2017.01); H01L 27/11556 (2017.01); H01L 27/11582 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); H01L 21/7682 (2013.01); H01L 21/76831 (2013.01); H01L 21/76834 (2013.01); H01L 23/5329 (2013.01); H01L 27/1157 (2013.01); H01L 27/11582 (2013.01); H01L 21/31053 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01);
Abstract

According to one embodiment, a semiconductor device includes a foundation layer, a stacked body provided above the foundation layer, a semiconductor body, and a charge storage portion. The stacked body includes a plurality of electrode layers stacked with an air gap interposed, a plurality of select gate layers stacked in a stacking direction of the electrode layers, and an insulating body provided between the select gate layers adjacent to each other in the stacking direction. The semiconductor body extends in the stacking direction in the stacked body. The charge storage portion is provided between the semiconductor body and one of the electrode layers.


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