The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 2019

Filed:

May. 15, 2017
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Gijs Jan de Raad, Gelderland, NL;

Da-Wei Lai, Nijmegen, NL;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H05K 9/00 (2006.01); H02H 9/04 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0248 (2013.01); H01L 27/0251 (2013.01); H01L 27/0259 (2013.01); H01L 27/0262 (2013.01); H01L 29/7833 (2013.01); H02H 9/046 (2013.01); H05K 9/0067 (2013.01);
Abstract

Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, an ESD protection device includes a bipolar transistor device connected between a first node and a second node, a series protection device connected in series with the bipolar transistor device, and a diode device connected between the second node and a third node. A drain terminal of an NMOS device to be protected is connectable to the first node. A body of the NMOS device to be protected is connectable to the second node. A source terminal of the NMOS device to be protected is connectable to the third node. The diode device and the bipolar transistor device are configured to form a parasitic silicon controlled rectifier. Other embodiments are also described.


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