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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10366886 B1

PDFFull Text
Expired
Date of Patent:
Jul. 30, 2019

Filed:

Feb. 28, 2017

Pattern forming method, self-organization material, and method of manufacturing semiconductor apparatus

Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Seiji Morita, Shinagawa Tokyo, JP;

Masahiro Kanno, Yokohama Kanagawa, JP;

Yusuke Kasahara, Yokohama Kanagawa, JP;

Assignee:

Toshiba Memory Corporation, Tokyo, JP;

Attorney:

Kim & Stewart LLP

Primary Examiner:

Shamim Ahmed

Int. Cl.
CPC ...
H01L 21/027 (2006.01); C09D 5/00 (2006.01); C08F 293/00 (2006.01); C09D 153/00 (2006.01); H01L 21/02 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0271 (2013.01); C08F 293/005 (2013.01); C09D 5/00 (2013.01); C09D 153/00 (2013.01); H01L 21/02118 (2013.01); H01L 21/31058 (2013.01); H01L 21/31138 (2013.01); H01L 21/31144 (2013.01);
Abstract

According to one embodiment, a pattern forming method includes supplying, onto an under layer, a self-organization material including a block copolymer which includes a first polymer and a second polymer, and a third polymer having a molecular structure with oxygen attached to a cyclic structure, wherein the third polymer is bonded to the first polymer, and phase-separating the block copolymer to form a phase-separation pattern on the under layer.

Find Patent Forward Citations

Morita, Seiji. (2019). Pattern forming method, self-organization material, and method of manufacturing semiconductor apparatus (U.S. Patent No. 10366886). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10366886

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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