The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 2019

Filed:

Nov. 20, 2017
Applicant:

Lam Research Corporation, Fremont, CA (US);

Inventors:

Scott Riggs, San Francisco, CA (US);

Ryan Bise, Campbell, CA (US);

John Valcore, Fremont, CA (US);

Eric Hudson, Berkley, CA (US);

Ranadeep Bhowmick, Fremont, CA (US);

Assignee:

Lam Research Corporation, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01J 37/32 (2006.01); G06F 1/12 (2006.01); G06F 1/08 (2006.01);
U.S. Cl.
CPC ...
H01J 37/3299 (2013.01); G06F 1/08 (2013.01); G06F 1/12 (2013.01);
Abstract

A communications system for synchronizing control signals between subsystems coupled to a process module used for processing a substrate. A distributed controller coupled to the subsystems is configured to initiate process steps, each step having a step period. A distributed clock module includes a master clock having a clock speed including clock cycles, each clock cycle having a duration that is pre-correlated to a feedback loop within which synchronized control signals are delivered to and received from the subsystems by the distributed clock module. A predefined number of clock cycles is assigned by the distributed clock module for performing a corresponding number of feedback loops for transitioning between process steps. The predefined number of clock cycles are restricted to a fraction of the step period.


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