The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 30, 2019
Filed:
May. 01, 2017
Applicant:
Nvidia Corporation, Santa Clara, CA (US);
Inventors:
John R. Nickolls, Los Altos, CA (US);
Brett W. Coon, San Jose, CA (US);
Michael C. Shebanow, Saratoga, CA (US);
Assignee:
NVIDIA CORPORATION, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01); G06F 9/38 (2018.01); G06F 12/0811 (2016.01); G06F 12/0862 (2016.01); G06F 12/121 (2016.01); G06F 9/30 (2018.01); G06F 12/0875 (2016.01); G06F 12/0897 (2016.01); G06F 12/0871 (2016.01);
U.S. Cl.
CPC ...
G06F 9/3887 (2013.01); G06F 9/3009 (2013.01); G06F 9/30043 (2013.01); G06F 9/3836 (2013.01); G06F 12/0811 (2013.01); G06F 12/0862 (2013.01); G06F 12/0875 (2013.01); G06F 12/0897 (2013.01); G06F 12/121 (2013.01); G06F 12/0871 (2013.01); G06F 2212/452 (2013.01);
Abstract
A technique for managing a parallel cache hierarchy that includes receiving an instruction from a scheduler unit, where the instruction comprises a load instruction or a store instruction; determining that the instruction includes a cache operations modifier that identifies a policy for caching data associated with the instruction at one or more levels of the parallel cache hierarchy; and executing the instruction and caching the data associated with the instruction based on the cache operations modifier.