The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 30, 2019
Filed:
Feb. 01, 2017
Applicant:
Toshiba Memory Corporation, Minato-ku, JP;
Inventors:
Yoshihisa Kojima, Kawasaki, JP;
Katsuhiko Ueki, Katsushika, JP;
Assignee:
TOSHIBA MEMORY CORPORATION, Minato-ku, JP;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/06 (2006.01); G06F 13/16 (2006.01); G06F 12/02 (2006.01); G11C 7/10 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0613 (2013.01); G06F 3/064 (2013.01); G06F 3/0659 (2013.01); G06F 3/0688 (2013.01); G06F 12/0246 (2013.01); G06F 12/0607 (2013.01); G06F 13/1647 (2013.01); G11C 7/1042 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/3427 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/7208 (2013.01);
Abstract
According to one embodiment, a controller executes a first process such that writing is performed in an order of page numbers in the memory chip. The first process includes a second process to be executed in an order of group units. The second process includes a process of writing data to the lower pages of the memory chips belonging to the banks in one group, and subsequently writing data to the upper pages of the memory chips belonging to the banks in the group.