Multiprocessor system having fast clocking prefetch circuits that cause processor clock signals to be gapped

Abstract

A multiprocessor system includes several processors, a prefetching instruction code interface block, a prefetching data code interface block, a Shared Local Memory (SLMEM), and Clock Gapping Circuits (CGCs). Each processor has the same address map. Each fetches instructions from SLMEM via the instruction interface block. Each accesses data from/to SLMEM via the data interface block. The interface blocks and the SLMEM are clocked at a faster rate than the processors. The interface blocks have wide prefetch lines of the width of the SLMEM. The data interface block supports no-wait single-byte data writes from the processors, and also supports no-wait multi-byte data writes. An address translator prevents one processor from overwriting the stack of another. If a requested instruction or data is not available in the appropriate prefetching circuit, then the clock signal of the requesting processor is gapped until the instruction or data can be returned to the requesting processor.