The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 2019

Filed:

Jun. 29, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Jian Sun, Shanghai, CN;

Chao Meng, Shanghai, CN;

Xiaoxiao Li, Shanghai, CN;

Yinpeng Lu, Shanghai, CN;

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/00 (2006.01); G01R 31/3185 (2006.01); G11C 29/30 (2006.01); G06F 11/22 (2006.01); H03K 19/177 (2006.01); H03K 19/173 (2006.01); G11C 29/12 (2006.01); G11C 29/32 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318536 (2013.01); G01R 31/318505 (2013.01); G06F 11/2205 (2013.01); G11C 29/12015 (2013.01); G11C 29/30 (2013.01); G11C 29/32 (2013.01); H03K 19/1735 (2013.01); H03K 19/1776 (2013.01); G11C 2029/3202 (2013.01);
Abstract

A register array includes a plurality of groups of latches. Each of the groups of latches includes a first latch, a second latch, and a test latch connected to the first latch and the second latch. During functional operation the first latch and the second latch process data, in response to the same read/write clock signal supplied simultaneously to the first read/write clock input and the second read/write clock input. During test operation a skewed test clock signal of an original test clock signal is supplied at different timings to the first latch, the second latch, and the test latch, and a single scan signal is input to the first latch. The single scan signal cascades from the first latch through the test latch to the second latch, and is output by the second latch, within a single cycle of the original test clock signal.


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