The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2019

Filed:

Jul. 25, 2018
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Kazuhiro Tomita, Kasugai, JP;

Masuo Inui, Aichi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 15/02 (2006.01); H04L 12/40 (2006.01); H04L 7/00 (2006.01); H04L 25/49 (2006.01); H04B 15/00 (2006.01); H04B 1/3822 (2015.01);
U.S. Cl.
CPC ...
H04B 15/02 (2013.01); H04B 1/3822 (2013.01); H04B 15/005 (2013.01); H04L 7/0012 (2013.01); H04L 7/0037 (2013.01); H04L 12/40006 (2013.01); H04L 25/4902 (2013.01); H04L 25/4906 (2013.01);
Abstract

An example embodiment provides a transceiver for communication includes a timing determiner that detects a fall from high level to low level of a bus signal generated by pulse width modulation of a clock signal and input from a communication bus; a transmission data signal delay adjuster that determines a second timing having a predetermined time difference from a first timing, the bus signal rising from the low level to the high level at the first timing; an encoder that extends a low level of the bus signal by changing a data signal to be output to the communication bus from high level to low level; and a timing adjustment circuit that changes the data signal to the low level at the second timing.


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