The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2019

Filed:

May. 24, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Sidharth Rastogi, Hwaseong-si, KR;

Subhash Kuchanuri, Hwaseong-si, KR;

Raheel Azmat, Suwon-si, KR;

Pan-jae Park, Seongnam-si, KR;

Chul-hong Park, Seongnam-si, KR;

Jae-seok Yang, Hwaseong-si, KR;

Kwan-young Chun, Suwon-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 23/535 (2006.01); H01L 29/06 (2006.01); H01L 29/49 (2006.01); H01L 27/02 (2006.01); H01L 29/78 (2006.01); H01L 29/417 (2006.01); H01L 21/8238 (2006.01); H01L 27/118 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 23/535 (2013.01); H01L 27/0207 (2013.01); H01L 27/0924 (2013.01); H01L 29/0642 (2013.01); H01L 29/0649 (2013.01); H01L 29/4966 (2013.01); H01L 21/823828 (2013.01); H01L 21/823871 (2013.01); H01L 29/41791 (2013.01); H01L 29/785 (2013.01); H01L 2027/11829 (2013.01);
Abstract

An integrated circuit device includes a substrate including a fin active region extending in a first direction, a gate line intersecting the fin active region and extending in a second direction perpendicular to the first direction, a power line electrically connected to source/drain regions at sides of the gate line on the fin active region, a pair of dummy gate lines intersecting the fin active region and extending in the second direction, and a device separation structure electrically connected to the pair of dummy gate lines and including a lower dummy contact plug between the pair of dummy gate lines on the fin active region and electrically connected to the power line, and an upper dummy contact plug on the lower dummy contact plug and on the pair of dummy gate lines to electrically connect the lower dummy contact plug to the pair of dummy gate lines.


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