The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2019

Filed:

Apr. 18, 2018
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Ryo Kanda, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 29/08 (2006.01); H01L 21/02 (2006.01); H01L 29/43 (2006.01); H01L 29/739 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0623 (2013.01); H01L 21/02164 (2013.01); H01L 29/0804 (2013.01); H01L 29/42304 (2013.01); H01L 29/435 (2013.01); H01L 29/66325 (2013.01); H01L 29/7397 (2013.01); H01L 29/4232 (2013.01); H01L 29/7393 (2013.01); H01L 2924/13055 (2013.01);
Abstract

According to one embodiment, a semiconductor device includes a semiconductor substrate, a trench electrode provided in a trench, a trench insulating film provided between the trench electrode and the semiconductor substrate, a MOS electrode provided near the trench electrode, and a MOS insulating film provided between the MOS electrode and the semiconductor substrate, in which the semiconductor substrate includes a first semiconductor layer, a second semiconductor layer provided over the first semiconductor layer, a third semiconductor layer provided over the second semiconductor layer, a fourth semiconductor layer provided below the MOS electrode, and one and the other of fifth semiconductor layers provided on both sides of the fourth semiconductor layer, and in which the semiconductor device further includes a wiring layer that couples the one of the fifth semiconductor layers and the second semiconductor layer together.


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