The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 23, 2019
Filed:
Apr. 20, 2016
Applicant:
Stmicroelectronics (Crolles 2) Sas, Crolles, FR;
Inventor:
Jean Jimenez, Salles d'Aude, FR;
Assignee:
STMicroelectronics (Crolles 2) SAS, Crolles, FR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 29/66 (2006.01); H01L 27/082 (2006.01); H01L 27/092 (2006.01); H01L 29/732 (2006.01); H01L 29/808 (2006.01); H01L 21/8228 (2006.01); H01L 21/8238 (2006.01); H01L 21/8249 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0623 (2013.01); H01L 21/8249 (2013.01); H01L 21/82285 (2013.01); H01L 21/823885 (2013.01); H01L 27/0826 (2013.01); H01L 27/092 (2013.01); H01L 29/66909 (2013.01); H01L 29/732 (2013.01); H01L 29/8083 (2013.01);
Abstract
An integrated circuit of the BiCMOS type includes at least one vertical junction field-effect transistor. The vertical junction field-effect transistor is formed to include a channel region having a critical dimension of active surface that is controlled by photolithography.
Jimenez, Jean. (2019). Method for fabricating a jfet transistor within an integrated circuit and corresponding integrated circuit (U.S. Patent No. 10361188). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10361188
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile