The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2019

Filed:

Jun. 28, 2018
Applicant:

Ford Global Technologies, Llc, Dearborn, MI (US);

Inventors:

Zhuxian Xu, Novi, MI (US);

Nevin Altunyurt, Atlanta, GA (US);

Chingchi Chen, Ann Arbor, MI (US);

Assignee:

FORD GLOBAL TECHNOLOGIES, LLC, Dearborn, MI (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H02M 7/00 (2006.01); H01L 23/00 (2006.01); H01L 23/367 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49562 (2013.01); H01L 23/367 (2013.01); H01L 23/4952 (2013.01); H01L 23/49575 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/49 (2013.01); H02M 7/003 (2013.01); H01L 2224/05553 (2013.01); H01L 2224/48247 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/14252 (2013.01);
Abstract

A power module has upper and lower transistor dies carried by a lead frame assembly. The assembly has a positive DC paddle for the upper die and an AC paddle for the lower die. An upper plate interconnects a second side of the upper die with the AC paddle, and a lower plate interconnects a second side of the lower die with a negative power bar. Current flowing via positive and negative power bars defines a power loop creating a main magnetic flux with a first direction in a central region and a return direction outside the central region. The upper and lower plates have outer edges having respective notches to concentrate respective portions of a return magnetic flux. Each die has a gate pad connected in a gate loop, wherein the gate loops each overlap a respective concentrated return flux thereby enhancing a common source inductance for each transistor.


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