The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2019

Filed:

Sep. 12, 2017
Applicant:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

Inventors:

Yasuhiro Suematsu, Yokohama Kanagawa, JP;

Masaru Koyanagi, Tokyo, JP;

Satoshi Inoue, Zushi Kanagawa, JP;

Kenro Kubota, Yokohama Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/06 (2006.01); G11C 16/08 (2006.01); H01L 27/11526 (2017.01); H01L 27/11573 (2017.01); G11C 16/24 (2006.01); H01L 23/528 (2006.01); G11C 7/10 (2006.01); G11C 16/26 (2006.01); H01L 27/02 (2006.01); H01L 27/092 (2006.01); G11C 16/04 (2006.01); G11C 16/30 (2006.01);
U.S. Cl.
CPC ...
G11C 16/08 (2013.01); G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); H01L 23/528 (2013.01); H01L 27/11526 (2013.01); H01L 27/11573 (2013.01); G11C 16/0483 (2013.01); G11C 16/30 (2013.01); G11C 2207/105 (2013.01); H01L 27/0207 (2013.01); H01L 27/092 (2013.01);
Abstract

The present embodiment discloses a semiconductor memory device which includes a memory cell array, a signal pad, a first voltage pad, a first regulation circuit and a first operation circuit. The signal pad supplies an output signal associated with the memory cell array. The first voltage pad receives a first voltage. The first regulation circuit regulates a signal output from the signal pad. The first operation circuit operates the first regulation circuit. The first regulation circuit and the first operation circuit are provided between the signal pad and the first voltage pad.


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