The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2019

Filed:

Jun. 08, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

John K. DeBrosse, Colchester, VT (US);

Yutaka Nakamura, Kita-ku, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 8/08 (2006.01); G11C 11/408 (2006.01); G11C 11/22 (2006.01); G11C 11/16 (2006.01); G11C 13/00 (2006.01); G11C 16/08 (2006.01); G11C 16/04 (2006.01); G11C 5/14 (2006.01);
U.S. Cl.
CPC ...
G11C 8/08 (2013.01); G11C 11/1657 (2013.01); G11C 11/2257 (2013.01); G11C 11/4085 (2013.01); G11C 13/0028 (2013.01); G11C 16/08 (2013.01); G11C 5/147 (2013.01); G11C 13/0004 (2013.01); G11C 16/0408 (2013.01);
Abstract

A method includes applying a first voltage to a source of a first p-channel FET connected in series with a second p-channel FET, applying a second voltage, lower than the first voltage, to a source of a third p-channel FET connected in series with a fourth p-channel FET, applying a third voltage, lower than the first and second voltages, to a source of a second n-channel FET connected in series with a first n-channel FET, drains of the second p-channel FET, the fourth p-channel FET, and the first n-channel FET connect at a connection point including an output terminal for outputting an output signal, and outputting one of the first voltage, the second voltage, and the third voltage from the output terminal based on input signals inputted to corresponding gates of the first p-channel FET, the third p-channel FET, the fourth p-channel FET, and the second n-channel FET.


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