The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2019

Filed:

Apr. 02, 2018
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Hiroyuki Yamasaki, Tokyo, JP;

Hideyuki Noda, Tokyo, JP;

Kan Murata, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 13/40 (2006.01); G06F 13/36 (2006.01); G06F 9/38 (2018.01); G05B 19/042 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3001 (2013.01); G05B 19/0426 (2013.01); G06F 9/3005 (2013.01); G06F 9/3851 (2013.01); G06F 13/36 (2013.01); G06F 13/4068 (2013.01); G05B 2219/2207 (2013.01);
Abstract

Provided is a signal processing circuit occupying a small circuit area. A common arithmetic operation element is shared between a plurality of arithmetic operation sequence control units. An arbitration circuit selects, when the plurality of arithmetic operation sequence control units simultaneously generate requests for arithmetic operations to use the common arithmetic operation element, the predetermined sequence control unit based on priority information about the plurality of arithmetic operation sequence control units, causes the common arithmetic operation element to execute the arithmetic operation requested from the selected arithmetic operation sequence control unit, and returns the result of the arithmetic operation to the selected arithmetic operation sequence control unit.


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