The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2019

Filed:

Jan. 06, 2017
Applicant:

Montana Systems Inc., Rolling Hills Estates, CA (US);

Inventors:

Vivian Chou, Rancho Palos Verdes, CA (US);

Julien Lamoureux, Vancouver, CA;

Sherman Lee, Rancho Palos Verdes, CA (US);

Assignee:

Montana Systems Inc., Rolling Hills Estates, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2018.01); G06F 17/50 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3001 (2013.01); G06F 9/30145 (2013.01); G06F 9/3802 (2013.01); G06F 9/3851 (2013.01); G06F 9/3885 (2013.01); G06F 12/023 (2013.01); G06F 17/5022 (2013.01); G06F 17/5027 (2013.01); G06F 17/5036 (2013.01); G06F 17/5068 (2013.01); G06F 2212/251 (2013.01);
Abstract

A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.


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