The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2019

Filed:

Sep. 12, 2014
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Mikihiko Ito, Ota, JP;

Masaru Koyanagi, Ota, JP;

Shintaro Hayashi, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 3/06 (2006.01); G11C 29/12 (2006.01); G06F 1/3287 (2019.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); G11C 5/02 (2006.01); G11C 29/02 (2006.01); G11C 29/48 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0635 (2013.01); G06F 1/3287 (2013.01); G06F 3/0625 (2013.01); G06F 3/0656 (2013.01); G06F 3/0683 (2013.01); G06F 13/1673 (2013.01); G06F 13/4022 (2013.01); G06F 13/4282 (2013.01); G11C 5/025 (2013.01); G11C 29/021 (2013.01); G11C 29/12 (2013.01); G11C 29/1201 (2013.01); G11C 29/48 (2013.01);
Abstract

According to one embodiment, there is provided a storage device including a control chip and a plurality of memory chips. The control chip has an input buffer common to the control chip and the plurality of memory chips and electrically connected to an external terminal. A first transmission path going through the input buffer and a second transmission path not going through the input buffer are provided between the external terminal and the plurality of memory chips. In a first mode, the control chip enables the input buffer so as to activate the first transmission path and, in a second mode, disables the input buffer so as to activate the second transmission path.


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