The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2019

Filed:

Jun. 06, 2017
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Karin Inbar, Ramat-Hasharon, IL;

Michael Ionin, Rehovot, IL;

Einat Zevulun, Kfar-Sava, IL;

Einat Lev, Rehovot, IL;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 3/06 (2006.01); G06F 11/14 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0619 (2013.01); G06F 3/061 (2013.01); G06F 3/0613 (2013.01); G06F 3/0646 (2013.01); G06F 3/0658 (2013.01); G06F 3/0679 (2013.01); G06F 11/14 (2013.01); G06F 12/0246 (2013.01);
Abstract

An apparatus includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes a volatile memory configured to store a first copy of a control table associated with the non-volatile memory. The controller is configured to perform a first update of a portion of the first copy of the control table in response to a first request, to initiate a second update of a second copy of the control table at the non-volatile memory based on the first update, and to execute a second request for access to the non-volatile memory concurrently with of the second update. The controller is configured to perform non-blocking control sync operations and non-blocking consolidation operations asynchronously, wherein non-blocking consolidation operations are atomic operations that include concurrent evacuation and compaction of an update layer to a cached address translation table in the volatile memory.


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